Integrated circuits are typically formed on a semiconductor substrate such as a silicon wafer or other semiconducting material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. By way of example, the various materials are doped, ion implanted, deposited, etched, grown, etc. using various processes. A continuing goal in semiconductor processing is to continue to strive to reduce the size of individual electronic components thereby enabling smaller and denser integrated circuitry.
One technique for patterning and processing semiconductor substrates is photolithography. Such typically includes deposition of a photoresist layer which can then be processed to modify the solubility of such layer in certain solvents. For example, portions of the photoresist layer can be exposed to actinic energy through a mask/reticle to change the solvent solubility of the exposed regions versus the unexposed regions compared to the solubility in the as-deposited state. Thereafter, the exposed or unexposed portions can be removed, depending on the type of photoresist, thereby leaving a masking pattern of the photoresist on the substrate. Adjacent areas of the substrate next to the masked portions can be processed, for example by etching or ion implanting, to effect the desired processing of the substrate adjacent the masking material.
In certain instances, multiple different layers of photoresist are utilized in a given masking/photolithographic step. Further, the photolithographic masking and patterning might be combined with one or more other layers. One such process forms what is commonly referred to as a “hard mask” over the substrate prior to deposition of the photoresist layer or layers. The resist layer is then patterned, for example as described above, to form masking blocks over the hard mask. The hard mask is then etched using the photoresist as a mask to transfer the pattern of the photoresist to the hard mask. The resist may or may not be removed immediately thereafter. Hard masks such as just described provide a more robust masking pattern than using resist alone, for example should the resist be completely eroded/etched away during an etch.
One material utilized as a hard mask is amorphous carbon. When etching oxide material using amorphous carbon as a hard mask, the etching typically removes the oxide at a rate of about ten times faster than it removes amorphous carbon.
Other masking methods exist in addition to photolithographic processing such as described above. For example, field effect transistors utilize a conductive gate which is typically received over a channel region of semiconductive material. Conductively doped source/drain semiconductive material regions are typically received on opposing sides of the channel region, with the gate overlying or underlying such channel region therebetween. In certain instances, it is desirable that the doping profile across the source/drain region be lighter/lower more proximate the channel region than distal therefrom. One method of processing for providing such dopant profile is to first form a desired conductive gate outline over the desired channel region of a semiconductor substrate. A suitable implant dose of a conductivity enhancing impurity can then be provided into the semiconductive material of the substrate, with the gate construction precluding such implant into the channel region. Then, an insulating layer can be conformally deposited over the gate construction and anisotropically etched to form insulative sidewall spacers over the gate. These sidewall spacers effectively function as a mask which both protects the sidewalls of the gate and precludes a subsequent implant from occurring beneath the spacers just formed. Accordingly, the sidewall spacers can be used as a mask for a subsequent higher dose source/drain implant to complete the formation of the outline of the desired source/drain regions.
While the invention was motivated in addressing the above issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded (without interpretative or other limiting reference to the above background art description, remaining portions of the specification or the drawings) and in accordance with the doctrine of equivalents.